3 Commits

Author SHA1 Message Date
31a3772bcb spi psram works 2025-10-14 14:07:58 -06:00
212077578c Merge branch 'main' into psram-alloc 2025-10-14 12:43:26 -06:00
13d267f61e can alloc with psram 2025-06-26 20:34:18 -06:00
4 changed files with 552 additions and 143 deletions

263
Cargo.lock generated
View File

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version = "1.0.18"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "f63a545481291138910575129486daeaf8ac54aee4387fe7906919f7830c7d9d"
checksum = "5a5f39404a5da50712a4c1eecf25e90dd62b613502b7e925fd4e4d19b5c96512"
[[package]]
name = "unicode-width"
@@ -2602,9 +2610,9 @@ dependencies = [
[[package]]
name = "uuid"
version = "1.18.1"
version = "1.17.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "2f87b8aa10b915a06587d0dec516c282ff295b475d94abf425d62b57710070a2"
checksum = "3cf4199d1e5d15ddd86a694e4d0dffa9c323ce759fea589f00fef9d81cc1931d"
dependencies = [
"js-sys",
"wasm-bindgen",
@@ -2653,15 +2661,6 @@ version = "0.11.1+wasi-snapshot-preview1"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "ccf3ec651a847eb01de73ccad15eb7d99f80485de043efb2f370cd654f4ea44b"
[[package]]
name = "wasi"
version = "0.14.7+wasi-0.2.4"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "883478de20367e224c0090af9cf5f9fa85bed63a95c1abf3afc5c083ebc06e8c"
dependencies = [
"wasip2",
]
[[package]]
name = "wasip2"
version = "1.0.1+wasi-0.2.4"
@@ -2673,36 +2672,35 @@ dependencies = [
[[package]]
name = "wasm-bindgen"
version = "0.2.103"
version = "0.2.100"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "ab10a69fbd0a177f5f649ad4d8d3305499c42bab9aef2f7ff592d0ec8f833819"
checksum = "1edc8929d7499fc4e8f0be2262a241556cfc54a0bea223790e71446f2aab1ef5"
dependencies = [
"cfg-if",
"once_cell",
"rustversion",
"wasm-bindgen-macro",
"wasm-bindgen-shared",
]
[[package]]
name = "wasm-bindgen-backend"
version = "0.2.103"
version = "0.2.100"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "0bb702423545a6007bbc368fde243ba47ca275e549c8a28617f56f6ba53b1d1c"
checksum = "2f0a0651a5c2bc21487bde11ee802ccaf4c51935d0d3d42a6101f98161700bc6"
dependencies = [
"bumpalo",
"log",
"proc-macro2",
"quote",
"syn 2.0.106",
"syn 2.0.104",
"wasm-bindgen-shared",
]
[[package]]
name = "wasm-bindgen-macro"
version = "0.2.103"
version = "0.2.100"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "fc65f4f411d91494355917b605e1480033152658d71f722a90647f56a70c88a0"
checksum = "7fe63fc6d09ed3792bd0897b314f53de8e16568c2b3f7982f468c0bf9bd0b407"
dependencies = [
"quote",
"wasm-bindgen-macro-support",
@@ -2710,22 +2708,22 @@ dependencies = [
[[package]]
name = "wasm-bindgen-macro-support"
version = "0.2.103"
version = "0.2.100"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "ffc003a991398a8ee604a401e194b6b3a39677b3173d6e74495eb51b82e99a32"
checksum = "8ae87ea40c9f689fc23f209965b6fb8a99ad69aeeb0231408be24920604395de"
dependencies = [
"proc-macro2",
"quote",
"syn 2.0.106",
"syn 2.0.104",
"wasm-bindgen-backend",
"wasm-bindgen-shared",
]
[[package]]
name = "wasm-bindgen-shared"
version = "0.2.103"
version = "0.2.100"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "293c37f4efa430ca14db3721dfbe48d8c33308096bd44d80ebaa775ab71ba1cf"
checksum = "1a05d73b933a847d6cccdda8f838a22ff101ad9bf93e33684f39c1f5f0eece3d"
dependencies = [
"unicode-ident",
]
@@ -2748,11 +2746,11 @@ checksum = "ac3b87c63620426dd9b991e5ce0329eff545bccbbb34f3be09ff6fb6ab51b7b6"
[[package]]
name = "winapi-util"
version = "0.1.11"
version = "0.1.9"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "c2a7b1c03c876122aa43f3020e6c3c3ee5c05081c9a00739faf7503aeba10d22"
checksum = "cf221c93e13a30d793f7645a0e7762c55d169dbb0a49671918a2319d289b10bb"
dependencies = [
"windows-sys 0.61.0",
"windows-sys",
]
[[package]]
@@ -2761,12 +2759,6 @@ version = "0.4.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "712e227841d057c1ee1cd2fb22fa7e5a5461ae8e48fa2ca79ec42cfc1931183f"
[[package]]
name = "windows-link"
version = "0.2.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "45e46c0661abb7180e7b9c281db115305d49ca1709ab8242adf09666d2173c65"
[[package]]
name = "windows-sys"
version = "0.59.0"
@@ -2776,15 +2768,6 @@ dependencies = [
"windows-targets",
]
[[package]]
name = "windows-sys"
version = "0.61.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "e201184e40b2ede64bc2ea34968b28e33622acdbbf37104f0e4a33f7abe657aa"
dependencies = [
"windows-link",
]
[[package]]
name = "windows-targets"
version = "0.52.6"
@@ -2866,20 +2849,20 @@ dependencies = [
[[package]]
name = "zerocopy"
version = "0.8.27"
version = "0.8.26"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "0894878a5fa3edfd6da3f88c4805f4c8558e2b996227a3d864f47fe11e38282c"
checksum = "1039dd0d3c310cf05de012d8a39ff557cb0d23087fd44cad61df08fc31907a2f"
dependencies = [
"zerocopy-derive",
]
[[package]]
name = "zerocopy-derive"
version = "0.8.27"
version = "0.8.26"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "88d2b8d9c68ad2b9e4340d7832716a4d21a22a1154777ad56ea55c51a9cf3831"
checksum = "9ecf5b4cc5364572d7f4c329661bcc82724222973f2cab6f050a4e5c22f75181"
dependencies = [
"proc-macro2",
"quote",
"syn 2.0.106",
"syn 2.0.104",
]

View File

@@ -58,6 +58,7 @@ cyw43 = { version = "0.3.0", features = [
], optional = true }
cyw43-pio = { version = "0.3.0", optional = true }
critical-section = "1.2.0"
embedded-hal-bus = { version = "0.3.0", features = ["async"] }
embedded-hal = "0.2.7"
embedded-hal_2 = { package = "embedded-hal", version = "1.0.0" }

View File

@@ -11,6 +11,7 @@ mod display;
mod elf;
mod framebuffer;
mod peripherals;
mod psram;
mod scsi;
mod storage;
mod ui;
@@ -24,6 +25,7 @@ use crate::{
conf_peripherals,
keyboard::{KeyState, read_keyboard_fifo},
},
psram::init_psram,
scsi::MSC_SHUTDOWN,
storage::{SDCARD, SdCard},
ui::{SELECTIONS, clear_selection, ui_handler},
@@ -47,9 +49,11 @@ use embassy_rp::{
i2c::{self, I2c},
multicore::{Stack, spawn_core1},
peripherals::{
DMA_CH0, DMA_CH1, I2C1, PIN_6, PIN_7, PIN_10, PIN_11, PIN_12, PIN_13, PIN_14, PIN_15,
PIN_16, PIN_17, PIN_18, PIN_19, PIN_22, SPI0, SPI1, USB,
DMA_CH0, DMA_CH1, DMA_CH3, DMA_CH4, I2C1, PIN_2, PIN_3, PIN_6, PIN_7, PIN_10, PIN_11,
PIN_12, PIN_13, PIN_14, PIN_15, PIN_16, PIN_17, PIN_18, PIN_19, PIN_20, PIN_21, PIN_22,
PIO0, SPI0, SPI1, USB,
},
pio,
spi::{self, Spi},
usb as embassy_rp_usb,
};
@@ -65,6 +69,7 @@ use talc::*;
embassy_rp::bind_interrupts!(struct Irqs {
I2C1_IRQ => i2c::InterruptHandler<I2C1>;
USBCTRL_IRQ => embassy_rp_usb::InterruptHandler<USB>;
PIO0_IRQ_0 => pio::InterruptHandler<PIO0>;
});
static mut CORE1_STACK: Stack<16384> = Stack::new();
@@ -113,13 +118,24 @@ async fn main(_spawner: Spawner) {
cs: p.PIN_17,
det: p.PIN_22,
};
let psram = Psram {
pio: p.PIO0,
sclk: p.PIN_21,
mosi: p.PIN_2,
miso: p.PIN_3,
cs: p.PIN_20,
dma1: p.DMA_CH3,
dma2: p.DMA_CH4,
};
let mcu = Mcu {
i2c: p.I2C1,
clk: p.PIN_7,
data: p.PIN_6,
};
let executor0 = EXECUTOR0.init(Executor::new());
executor0.run(|spawner| unwrap!(spawner.spawn(kernel_task(spawner, display, sd, mcu, p.USB))));
executor0.run(|spawner| {
unwrap!(spawner.spawn(kernel_task(spawner, display, sd, psram, mcu, p.USB)))
});
}
// One-slot channel to pass EntryFn from core1
@@ -177,6 +193,15 @@ struct Sd {
cs: Peri<'static, PIN_17>,
det: Peri<'static, PIN_22>,
}
struct Psram {
pio: Peri<'static, PIO0>,
sclk: Peri<'static, PIN_21>,
mosi: Peri<'static, PIN_2>,
miso: Peri<'static, PIN_3>,
cs: Peri<'static, PIN_20>,
dma1: Peri<'static, DMA_CH3>,
dma2: Peri<'static, DMA_CH4>,
}
struct Mcu {
i2c: Peri<'static, I2C1>,
clk: Peri<'static, PIN_7>,
@@ -207,6 +232,19 @@ async fn setup_display(display: Display, spawner: Spawner) {
spawner.spawn(display_handler(display)).unwrap();
}
async fn setup_psram(psram: Psram) {
let psram = init_psram(
psram.pio, psram.sclk, psram.mosi, psram.miso, psram.cs, psram.dma1, psram.dma2,
)
.await;
defmt::info!("psram size: {}", psram.size);
if psram.size == 0 {
defmt::info!("\u{1b}[1mExternal PSRAM was NOT found!\u{1b}[0m");
}
}
async fn setup_sd(sd: Sd) {
let mut config = spi::Config::default();
config.frequency = 400_000;
@@ -227,12 +265,14 @@ async fn kernel_task(
spawner: Spawner,
display: Display,
sd: Sd,
psram: Psram,
mcu: Mcu,
usb: Peri<'static, USB>,
) {
setup_mcu(mcu).await;
Timer::after_millis(250).await;
setup_display(display, spawner).await;
setup_psram(psram).await;
setup_sd(sd).await;
let _usb = embassy_rp_usb::Driver::new(usb, Irqs);

385
kernel/src/psram.rs Normal file
View File

@@ -0,0 +1,385 @@
// This whole file was taken from
// <https://github.com/wezterm/picocalc-wezterm/blob/8dcf8aae0598afdeaf0ed2ba50c39dea6e30c011/src/psram.rs>
//
use crate::Irqs;
use embassy_futures::yield_now;
use embassy_rp::Peri;
use embassy_rp::gpio::{Drive, SlewRate};
use embassy_rp::peripherals::{DMA_CH3, DMA_CH4, PIN_2, PIN_3, PIN_20, PIN_21, PIO0};
use embassy_rp::pio::program::pio_asm;
use embassy_rp::pio::{Config, Direction, Pio, ShiftDirection};
use embassy_rp::pio_programs::clock_divider::calculate_pio_clock_divider;
use embassy_time::{Duration, Instant, Timer};
// The physical connections in the picocalc schematic are:
// LABEL PICO ESP-PSRAM64H
// RAM_CS - PIN_20 CE (pulled up to 3v3 via 10kOhm)
// RAM_SCK - PIN_21 SCLK
// RAM_TX - PIN_2 SI/SIO0
// RAM_RX - PIN_3 SO/SIO1
// RAM_IO2 - PIN_4 SIO2 (QPI Mode)
// RAM_IO3 - PIN_5 SIO3 (QPI Mode)
#[allow(unused)]
const PSRAM_CMD_READ_ID: u8 = 0x9F;
const PSRAM_CMD_RSTEN: u8 = 0x66;
const PSRAM_CMD_RST: u8 = 0x99;
const PSRAM_CMD_WRITE: u8 = 0x02;
const PSRAM_CMD_FAST_READ: u8 = 0x0B;
#[allow(unused)]
const PSRAM_CMD_NOOP: u8 = 0xFF;
#[allow(unused)]
const PSRAM_KNOWN_GOOD_DIE_PASS: u8 = 0x5d;
const SPEED: u32 = 133_000_000;
pub struct PsRam {
sm: embassy_rp::pio::StateMachine<'static, PIO0, 0>,
tx_ch: Peri<'static, DMA_CH3>,
rx_ch: Peri<'static, DMA_CH4>,
pub size: u32,
}
impl PsRam {
pub async fn send_command(&mut self, cmd: &[u8], out: &mut [u8]) {
if out.is_empty() {
self.sm
.tx()
.dma_push(self.tx_ch.reborrow(), cmd, false)
.await;
} else {
let (rx, tx) = self.sm.rx_tx();
tx.dma_push(self.tx_ch.reborrow(), cmd, false).await;
rx.dma_pull(self.rx_ch.reborrow(), out, false).await;
}
}
pub async fn write(&mut self, mut addr: u32, mut data: &[u8]) {
// I haven't seen this work reliably over 24 bytes
const MAX_CHUNK: usize = 24;
while data.len() > 0 {
let to_write = data.len().min(MAX_CHUNK);
//defmt::info!("writing {to_write} @ {addr}");
#[rustfmt::skip]
let mut to_send = [
32 + (to_write as u8 * 8), // write address + data
0, // read 0 bits
PSRAM_CMD_WRITE,
((addr >> 16) & 0xff) as u8,
((addr >> 8) & 0xff) as u8,
(addr & 0xff) as u8,
// This sequence must be MAX_CHUNK in length
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
];
for (src, dst) in data.iter().zip(to_send.iter_mut().skip(6)) {
*dst = *src;
}
self.send_command(&to_send[0..6 + to_write], &mut []).await;
addr += to_write as u32;
data = &data[to_write..];
}
}
pub async fn read_id(&mut self) -> [u8; 3] {
let mut id = [0u8; 3];
#[rustfmt::skip]
self.send_command(
&[
32, // write 32 bits
3 * 8, // read 8 bytes = 64 bits
PSRAM_CMD_READ_ID,
// don't care: 24-bit "address"
0, 0, 0,
],
&mut id,
)
.await;
id
}
pub async fn read(&mut self, mut addr: u32, mut out: &mut [u8]) {
// Cannot get reliable reads above 4 bytes at a time.
// out[4] will always have a bit error
const MAX_CHUNK: usize = 4;
while out.len() > 0 {
let to_read = out.len().min(MAX_CHUNK);
//defmt::info!("reading {to_read} @ {addr}");
self.send_command(
&[
40, // write 40 bits
to_read as u8 * 8, // read n bytes
PSRAM_CMD_FAST_READ,
((addr >> 16) & 0xff) as u8,
((addr >> 8) & 0xff) as u8,
(addr & 0xff) as u8,
0, // 8 cycle delay by sending 8 bits of don't care data
],
&mut out[0..to_read],
)
.await;
addr += to_read as u32;
out = &mut out[to_read..];
}
}
#[allow(unused)]
pub async fn write8(&mut self, addr: u32, data: u8) {
//defmt::info!("write8 addr {addr} <- {data:x}");
self.send_command(
&[
40, // write 40 bits
0, // read 0 bits
PSRAM_CMD_WRITE,
((addr >> 16) & 0xff) as u8,
((addr >> 8) & 0xff) as u8,
(addr & 0xff) as u8,
data,
],
&mut [],
)
.await;
}
#[allow(unused)]
pub async fn read8(&mut self, addr: u32) -> u8 {
let mut buf = [0u8];
self.send_command(
&[
40, // write 40 bits
8, // read 8 bits
PSRAM_CMD_FAST_READ,
((addr >> 16) & 0xff) as u8,
((addr >> 8) & 0xff) as u8,
(addr & 0xff) as u8,
0, // 8 cycle delay
],
&mut buf,
)
.await;
buf[0]
}
}
pub async fn init_psram(
pio: Peri<'static, PIO0>,
sclk: Peri<'static, PIN_21>,
mosi: Peri<'static, PIN_2>,
miso: Peri<'static, PIN_3>,
cs: Peri<'static, PIN_20>,
dma1: Peri<'static, DMA_CH3>,
dma2: Peri<'static, DMA_CH4>,
) -> PsRam {
let mut pio = Pio::new(pio, Irqs);
let divider = calculate_pio_clock_divider(SPEED);
// This pio program was taken from
// <https://github.com/polpo/rp2040-psram/blob/7786c93ec8d02dbb4f94a2e99645b25fb4abc2db/psram_spi.pio>
// which is Copyright © 2023 Ian Scott, reproduced here under the MIT license
let p = pio_asm!(
r#"
.side_set 2 ; sideset bit 1 is SCK, bit 0 is CS
begin:
out x, 8 side 0b01 ; x = number of bits to output. CS deasserted
out y, 8 side 0b01 ; y = number of bits to input
jmp x--, writeloop side 0b01 ; Pre-decement x by 1 so loop has correct number of iterations
writeloop:
out pins, 1 side 0b00 ; Write value on pin, lower clock. CS asserted
jmp x--, writeloop side 0b10 ; Raise clock: this is when PSRAM reads the value. Loop if we have more to write
jmp !y, done side 0b00 ; If this is a write-only operation, jump back to beginning
nop side 0b10 ; Fudge factor of extra clock cycle; the PSRAM needs 1 extra for output to start appearing
jmp readloop_mid side 0b00 ; Jump to middle of readloop to decrement y and get right clock phase
readloop:
in pins, 1 side 0b00 ; Read value on pin, lower clock. Datasheet says to read on falling edge > 83MHz
readloop_mid:
jmp y--, readloop side 0b10 ; Raise clock. Loop if we have more to read
done:
nop side 0b11 ; CS deasserted
"#
);
let prog = pio.common.load_program(&p.program);
let mut cfg = Config::default();
let mut cs = pio.common.make_pio_pin(cs);
let mut sclk = pio.common.make_pio_pin(sclk);
let mut mosi = pio.common.make_pio_pin(mosi);
let mut miso = pio.common.make_pio_pin(miso);
sclk.set_slew_rate(SlewRate::Fast);
mosi.set_slew_rate(SlewRate::Fast);
cs.set_drive_strength(Drive::_4mA);
sclk.set_drive_strength(Drive::_4mA);
mosi.set_drive_strength(Drive::_4mA);
miso.set_drive_strength(Drive::_4mA);
cfg.use_program(&prog, &[&cs, &sclk]);
cfg.set_out_pins(&[&mosi]);
cfg.set_in_pins(&[&miso]);
cfg.shift_out.direction = ShiftDirection::Left;
cfg.shift_out.auto_fill = true;
cfg.shift_out.threshold = 8;
cfg.shift_in = cfg.shift_out;
cfg.clock_divider = divider;
let mut sm = pio.sm0;
sm.restart();
sm.set_pin_dirs(Direction::Out, &[&cs, &sclk]);
sm.set_pin_dirs(Direction::Out, &[&mosi]);
sm.set_pin_dirs(Direction::In, &[&miso]);
miso.set_input_sync_bypass(true);
sm.set_config(&cfg);
sm.set_enable(true);
let mut psram = PsRam {
sm,
tx_ch: dma1,
rx_ch: dma2,
size: 0,
};
// Issue a reset command
psram.send_command(&[8, 0, PSRAM_CMD_RSTEN], &mut []).await;
Timer::after(Duration::from_micros(50)).await;
psram.send_command(&[8, 0, PSRAM_CMD_RST], &mut []).await;
Timer::after(Duration::from_micros(100)).await;
defmt::info!("Verifying 1 byte write and read...");
for i in 0..10u8 {
psram.write8(i as u32, i).await;
}
for i in 0..10u32 {
let n = psram.read8(i as u32).await;
if n as u32 != i {}
}
defmt::info!("testing read again @ 0");
let mut got = [0u8; 8];
psram.read(0, &mut got).await;
const EXPECT: &[u8] = &[0, 1, 2, 3, 4, 5, 6, 7];
if got != EXPECT {
defmt::warn!("Got Read error");
}
const DEADBEEF: &[u8] = &[0xd, 0xe, 0xa, 0xd, 0xb, 0xe, 0xe, 0xf];
defmt::info!("testing write of deadbeef at 0");
psram.write(0, DEADBEEF).await;
defmt::info!("testing read of deadbeef from 0");
psram.read(0, &mut got).await;
if got != DEADBEEF {
for addr in 0..DEADBEEF.len() {
let bad = got[addr];
if bad != DEADBEEF[addr] {
let x = psram.read8(addr as u32).await;
defmt::info!("read addr: {}, got: {:X}", addr, x);
}
}
}
const TEST_STRING: &[u8] = b"hello there, this is a test, how is it?";
psram.write(16, TEST_STRING).await;
let mut buffer = [0u8; 42];
psram.read(16, &mut buffer).await;
let got = &buffer[0..TEST_STRING.len()];
if got != TEST_STRING {}
defmt::info!("PSRAM test complete");
let id = psram.read_id().await;
defmt::info!("psram id: {}", id);
// id: [d, 5d, 53, 15, 49, e3, 7c, 7b]
// id[0] -- manufacturer id
// id[1] -- "known good die" status
if id[1] == PSRAM_KNOWN_GOOD_DIE_PASS {
// See <https://github.com/espressif/esp-idf/blob/1c468f68259065ef51afd114605d9122f13d9d72/components/esp_psram/esp32/esp_psram_impl_quad.c#L67-L86>
// for information on deciding the size of ESP PSRAM chips,
// such as the one used in the picocalc
let size = match (id[2] >> 5) & 0x7 {
0 => 16,
1 => 32,
2 => 64,
_ => 0,
};
psram.size = size * 1024 * 1024 / 8;
}
psram
}
#[allow(unused)]
pub async fn test_psram(psram: &mut PsRam) -> bool {
const REPORT_CHUNK: u32 = 256 * 1024;
const BLOCK_SIZE: usize = 8;
let limit = psram.size; //.min(4 * 1024 * 1024);
let start = Instant::now();
fn expect(addr: u32) -> [u8; BLOCK_SIZE] {
[
!((addr >> 24 & 0xff) as u8),
!((addr >> 16 & 0xff) as u8),
!((addr >> 8 & 0xff) as u8),
!((addr & 0xff) as u8),
((addr >> 24 & 0xff) as u8),
((addr >> 16 & 0xff) as u8),
((addr >> 8 & 0xff) as u8),
((addr & 0xff) as u8),
]
}
for i in 0..limit / BLOCK_SIZE as u32 {
let addr = i * BLOCK_SIZE as u32;
let data = expect(addr);
psram.write(addr, &data).await;
if addr > 0 && addr % REPORT_CHUNK == 0 {
if start.elapsed() > Duration::from_secs(5) {}
}
// Yield so that the watchdog doesn't kick in
yield_now().await;
}
let writes_took = start.elapsed();
defmt::info!("Starting reads...");
Timer::after(Duration::from_millis(200)).await;
let start = Instant::now();
let mut bad_count = 0;
let mut data = [0u8; BLOCK_SIZE];
for i in 0..limit / BLOCK_SIZE as u32 {
let addr = i * BLOCK_SIZE as u32;
let expect = expect(addr);
psram.read(addr, &mut data).await;
if addr == 0 {
Timer::after(Duration::from_millis(200)).await;
}
if data != expect {
bad_count += 1;
if bad_count < 50 {}
}
if addr > 0 && addr % REPORT_CHUNK == 0 {
if start.elapsed() > Duration::from_secs(5) {}
}
// Yield so that the watchdog doesn't kick in
yield_now().await;
}
let reads_took = start.elapsed();
bad_count == 0
}